1. Field of the Invention
This invention relates to the field of semiconductor memory controllers and more particularly to a simplified method of managing electrically erasable programmable read only memory (EEPROM) and flash memory devices.
2. Description of the Relevant Art
Semiconductor memories can be generally categorized as either volatile or non-volatile. Volatile memories such as static and dynamic random access memories (RAMs) are characterized by fast cycle times for both read and write operations, random access for both read and write operations, and, in the case of dynamic RAMs, high density. For these reasons, volatile memories are highly desirable in many applications. As their name implies however, volatile memories are susceptible to power loss. RAMs retain their stored data only as long a constant DC voltage is maintained at the power supply pin of the device. On the other hand, non-volatile memories such as ROMs, PROMs, EPROMs, EEPROMs, and flash memories are immune to power failure; retaining their stored data whether power is applied or not.
The memory cell of a typical EEPROM or flash memory device is the floating gate transistor. The floating gate transistor has source and drain regions similar to a conventional MOS transistor, but the polysilicon (poly) gate is electrically unconnected to other circuitry within the device. This "floating" gate is formed over a thin oxide, which is usually less than 100 angstroms thick. The threshold voltage of the floating gate transistor is manipulated by controlling the quantity of electrons that reside on the floating gate. The source and drain regions of the floating gate cell are coupled and uncoupled through the use a control gate. The control gate can alternatively be fashioned as a second poly gate, formed over the floating gate and separated from the floating gate by a dielectric, or as a contact to the device channel. If a sufficient number of electrons are deposited on the floating gate, the control gate will be unable to turn on the transistor (i.e. the threshold voltage will exceed the operating voltage of the circuit). If the electrons deposited on the floating gate are subsequently removed, applying a voltage in the range of 2.4 to 6 Volts to the control gate will form a channel between the source and drain regions.
Typically, electrons are deposited on the floating gate of EEPROM and flash memory devices during a programming operation. During programming, the control gate and the drain are raised to highly positive values with respect to the source. The positive voltages on the gate and drain generate hot electrons in the channel near the drain. The hot electrons are injected onto the floating gate where they are trapped. To subsequently remove the trapped electrons from the floating gate, a relatively high voltage is applied to the source while the gate is grounded. The floating gate electrons drift toward the region of the floating gate over the highly doped source region where the high electric field across the oxide causes the floating gate electrons to tunnel from the gate to the source.
The programming time and erase time of EEPROM and flash memory devices are significantly greater than the write time of a RAM. Moreover, because EEPROM and flash memory cells must be erased prior to the programming or writing of new data, EEPROM and flash memories are not generally useful in applications requiring random access. In certain applications however, where data is accumulated, stored, and retrieved sequentially (such as in many audio applications), EEPROM and flash memory devices are a viable alternative to conventional RAMs and provide the added benefit of non-volatility. In applications where data is written only occasionally but read frequently, EEPROMs and flash memory devices provide densities and read access times comparable to those of RAMs and data storage that is immune to power failure.
Because EEPROMs and flash memories are not random access devices, it is typically necessary to provide an array controller when using them as a storage medium. Two restrictive characteristics of flash memory arrays make array controllers necessary. The first characteristic is that flash memory cells must be erased before they can be written. The second restriction is that flash memory cells cannot be individually erased, but are instead erased in large blocks referred to as sectors. Sector architecture speeds the time required to erase the entire array, but limits the flexibility of the device. In flash memory arrays, an array controller is provided to keep track of the available (i.e. erased) cells and to control the sector erase of the devices.
Prior art flash array management methods contain numerous drawbacks which limit their utility. U.S. Pat. No. 5,404,485 ("the '485 patent"), for example, discloses a virtual mapping system for a flash memory array that allows data to be continuously written to available/array address locations. Designed to enable a flash memory array to be used as a random access storage element, the '485 patent employs a level of overhead that can be eliminated in many applications. The '485 patent performs an elaborate sequence of translations to convert a virtual address into a physical address within a flash memory array. In the method disclosed in the '485 patent, a virtual address is first translated into a logical address and then translated into a physical address. The patent requires two translation steps because addressing of the memory array is accomplished with a block address and a unit address. The unit address changes during a memory update cycle while the block address remains the same.
It will be appreciated to those skilled in the art that the two step translation process required by the '485 slows memory access times and consumes valuable bus bandwidth. Moreover, the requirement that each sector or unit contain a block allocation map reduces the size of the flash memory array available for data storage. In addition, the block allocation map must be altered during a write operation requiring an additional programming cycle in each write cycle. Because programming cycles are generally on the order of 15 microseconds or more, frequent array updates require frequent alteration of the block allocation map slowing down the overall system. In addition, the method disclosed in the '485 patent requires that the virtual map be itself saved in RAM. By requiring that the mapping be saved in RAM, the '485 patent forfeits its immunity to power outages. In addition, conventional flash memory controllers frequently employ copy-erase-copy back procedures to perform updates. Such procedures unnecessarily increase the number of erase cycles thereby negatively impacting the device lifetime. In addition, conventional flash memory controllers use extensive tables or directories to monitor the status of the array. It is therefore desirable to design a method for managing a flash memory array that circumvents these drawbacks.